Abstract
Verifying the correct operation of hardware systems is a complicated, multifaceted task, which can be performed on several different levels:

• System architecture level
• Implementation level (IC)
• Logic gates level
• Transistor level, etc.

 Each of these levels requires a different approach for verifying the correctness of the system properties. At the logic gate level, for example, one can try and verify that two combinatorial or sequential circuits implement the same logic functions.
 At the more abstract architectural level, the individual components of the system are treated as building blocks, and the verification process involves checking their interactions with each other according to a set of pre-specified rules (a hardware protocol).
 In this paper, we present a system based upon Series Parallel Posets which can be used to model and analyze the behavior of non-iterated systems.