Abstract
The complexity of the instruction set of modern processors often leads to faults in the microinstruction sequencing, and timing errors, which are difficult to detect with conventional simulation methods. Formal verification offers a powerful alternative for dealing with these problems. In this paper we present a mathematical model of the microcode of a Transputer-like microprocessor, and demonstrate how to test for the satisfaction of desired properties and the absence of improper microinstruction sequencing. The verification is based on a recently introduced technique using the inductively defined notion of series parallel posets, which offers low time- and space complexity.